1. Field of Invention
This invention relates to a manufacturing a MOSFET, of high integrated semiconductor device and more particularly, to a method of manufacturing a MOSFET with LDD (Lightly Doped Drain) region.
2. Description of the Prior Art
In parallel with the emergence of high integrated semiconductor device, the integrity of chips increase while the channel length of transistor decreases. The decrease of channel length in transistor causes some problems associated with DIBL (drain induced barrier lowering), hot-carrier effect and short-channel effect. To overcome this, a MOSFET with LDD regions is being widely used.
With reference to FIG. 1 and FIG. 2A through FIG. 2D, the conventional method for forming a MOSFET with LDD will now be described.
FIG. 1 is a layout view illustrating aligned masks in order to manufacture a MOSFET with LDD regions , in which a gate electrode mask (60) is arranged perpendicular to an active mask (50), and the active mask (50) is overlapped with a source/drain implant mask (70) which is larger in width than the active mask (50).
FIG. 2A to 2D are cross-sectional views illustrated according to I--I of FIG. 1, in manufacturing a MOSFET with LDD regions fabricated by the existing technology.
As shown in FIG. 2A, a field oxide layer 1 providing isolation between devices is formed by LOCOS (local oxidation of silicon) process on a silicon substrate 10 having p-type impurity as the 1st conductive type which is not formed on the active region, a gate oxide layer 2 is formed on the silicon substrate of the active region, and a gate electrode 3 is formed on a predetermined region of both active region and field oxide layer 1 as is further illustrated by FIG. 2E which is a cross-sectional view corresponding to FIG. 2A but according to IV--IV of FIG. 1.
As shown in FIG. 2B, an oxide layer 4 is formed on the surface of the gate electrode 3, n-type impurity of low concentration as the 2nd conductive type is implanted to the silicon substrate 10 by ion implantation to form the LDD region 5, and an insulating layer 6, for example an oxide layer, is formed on the whole structure.
As shown in FIG. 2C, the insulating layer 6 is etched by anisotropic etch to form the spacer 7 at both side walls of the gate electrode 3. During this etching process, both gate oxide layer 2 on the silicon substrate 10 and oxide layer 4 on the gate electrode 3 are etched. An oxide layer 12 is formed on the exposed silicon substrate 10, and then photoresist is coated on the whole structure and patterned into photsoresist layer 8A using the source/drain implant mask 70. FIG. 2C also shows that the photoresist pattern 8A is overlapped on both gate electrode 3 and field oxide layer 1, and that during the anisotropic etch process, the etching causes some damages 9 to the edge of Bird's Beak of the field oxide film 1.
As shown in FIG. 2D, a source/drain region 11 is formed by implanting n-type impurity of high concentration as the 2nd conductive type into the LDD region 5, and the photoresist layer pattern 8A is removed. FIG. 2D also shows that during the implantation process of said impurity, the source/drain region 11 from the damaged area of the field oxide layer 1 is implanted at the outside of the LDD region 5 so that the shaping of the LDD region 5 is defined as abrupt junction.
The prior art has recognized disadvantages in that during the etching process to form the spacer at the side of the gate electrode, a part of Bird's Beak of the field oxide layer is etched at the overlapping site between the field oxide layer and LDD region. Therefore, during the process to form the source/drain by ion implantation of n+ or p+ impurity of high concentration hereafter, the impurity of high concentration at the etched site of Bird's Beak of the field oxide layer is implanted at the outside of the LDD region, thus the shaping of the LDD region is defined as abrupt junction. This abrupt junction, which acts electrically as an unstable factor, might weaken the breakdown voltage of a MOSFET or increase junctive leakage current.